77 citations · 208 across the 15 of their papers we have counts for
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cs.AR2024★ 1 cited
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Jason Blocklove, Shailja Thakur, Benjamin Tan +3
Traditionally, digital hardware designs are written in the Verilog hardware description language (HDL) and debugged manually by engineers. This can be time-consuming and error-pron…
cs.LG2024★ 7 cited
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil +4
Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) effici…