activity
20192023
most citedThe gem5 Simulator: Version 20.0+

16 citations · 22 across the 5 of their papers we have counts for

collaborators

5 papers

cs.AR2023

PIMSAB: A Processing-In-Memory System with Spatially-Aware Communication and Bit-Serial-Aware Computation

Aman Arora, Jian Weng, Siyuan Ma +2

Bit-serial Processing-In-Memory (PIM) is an attractive paradigm for accelerator architectures, for parallel workloads such as Deep Learning (DL), because of its capability to achie…

cs.AR2022

CoMeFa: Compute-in-Memory Blocks for FPGAs

Aman Arora, Tanmay Anand, Aatman Borda +4

Block RAMs (BRAMs) are the storage houses of FPGAs, providing extensive on-chip memory bandwidth to the compute units implemented using Logic Blocks (LBs) and Digital Signal Proces…

cs.AR2021

Compute RAMs: Adaptable Compute and Storage Blocks for DL-Optimized FPGAs

Aman Arora, Bagus Hanindhito, Lizy K. John

The configurable building blocks of current FPGAs -- Logic blocks (LBs), Digital Signal Processing (DSP) slices, and Block RAMs (BRAMs) -- make them efficient hardware accelerators…

cs.AR2020★ 16 cited

The gem5 Simulator: Version 20.0+

Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram +75

The open-source and community-supported gem5 simulator is one of the most popular tools for computer architecture research. This simulation infrastructure allows researchers to mod…

cs.LG2019★ 6 cited

Demystifying the MLPerf Benchmark Suite

Snehil Verma, Qinzhe Wu, Bagus Hanindhito +4

MLPerf, an emerging machine learning benchmark suite strives to cover a broad range of applications of machine learning. We present a study on its characteristics and how the MLPer…