16 citations · 16 across the 2 of their papers we have counts for
2 papers
cs.AR2024
An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators
Corentin Ferry, Nicolas Derumigny, Steven Derrien +1
Memory bandwidth is known to be a performance bottleneck for FPGA accelerators, especially when they deal with large multi-dimensional data-sets. A large body of work focuses on re…
cs.AR2020★ 16 cited
The gem5 Simulator: Version 20.0+
Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram +75
The open-source and community-supported gem5 simulator is one of the most popular tools for computer architecture research. This simulation infrastructure allows researchers to mod…