41 citations · 74 across the 6 of their papers we have counts for
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cs.AR2018
Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
Yuzhe Ma, Subhendu Roy, Jin Miao +2
In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flo…
cs.AR2018
Adaptive 3D-IC TSV Fault Tolerance Structure Generation
Song Chen, Qi Xu, Bei Yu
In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield and reliability is one of…