2 citations · 5 across the 17 of their papers we have counts for
18 papers
GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search
Ao Zhou, Jianlei Yang, Tong Qiao +4
Graph Neural Networks (GNNs) have emerged as the state-of-the-art graph learning method. However, achieving efficient GNN inference on edge devices poses significant challenges, li…
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures
Yingjie Qi, Jianlei Yang, Rubing Yang +5
Compute-in-memory (CIM) has emerged as a pivotal direction for accelerating workloads in the field of machine learning, such as Deep Neural Networks (DNNs). However, the effective…
MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator
Xiaolin He, Cenlin Duan, Yingjie Qi +2
Computing-in-Memory (CIM) architectures have emerged as a promising solution for accelerating Deep Neural Networks (DNNs) by mitigating data movement bottlenecks. However, realizin…
ACE-GNN: Adaptive GNN Co-Inference with System-Aware Scheduling in Dynamic Edge Environments
Ao Zhou, Jianlei Yang, Tong Qiao +5
The device-edge co-inference paradigm effectively bridges the gap between the high resource demands of Graph Neural Networks (GNNs) and limited device resources, making it a promis…
Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous Platforms
Tong Qiao, Ao Zhou, Yingjie Qi +4
Graph Neural Networks (GNNs) have been widely adopted due to their strong performance. However, GNN training often relies on expensive, high-performance computing platforms, limiti…
HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference
Cenlin Duan, Jianlei Yang, Rubing Yang +8
The deployment of large language models (LLMs) presents significant challenges due to their enormous memory footprints, low arithmetic intensity, and stringent latency requirements…
Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity
Cenlin Duan, Jianlei Yang, Yikun Wang +7
Processing-in-memory (PIM) is a transformative architectural paradigm designed to overcome the Von Neumann bottleneck. Among PIM architectures, digital SRAM-PIM emerges as a promis…
CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures
Yingjie Qi, Jianlei Yang, Yiou Wang +6
Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the "memory wall" bottleneck. However, th…
HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices
Ao Zhou, Jianlei Yang, Yingjie Qi +5
Graph Neural Networks (GNNs) are becoming increasingly popular for graph-based learning tasks such as point cloud processing due to their state-of-the-art (SOTA) performance. Never…
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration
Tong Qiao, Jianlei Yang, Yingjie Qi +5
Graph Neural Networks (GNNs) succeed significantly in many applications recently. However, balancing GNNs training runtime cost, memory consumption, and attainable accuracy for var…
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity
Cenlin Duan, Jianlei Yang, Yiou Wang +7
Bit-level sparsity in neural network models harbors immense untapped potential. Eliminating redundant calculations of randomly distributed zero-bits significantly boosts computatio…
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems
Ao Zhou, Jianlei Yang, Tong Qiao +4
The key to device-edge co-inference paradigm is to partition models into computation-friendly and computation-intensive parts across the device and the edge, respectively. However,…
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory
Cenlin Duan, Jianlei Yang, Xiaolin He +9
Processing-in-memory (PIM), as a novel computing paradigm, provides significant performance benefits from the aspect of effective data movement reduction. SRAM-based PIM has been d…
Architectural Implications of GNN Aggregation Programming Abstractions
Yingjie Qi, Jianlei Yang, Ao Zhou +2
Graph neural networks (GNNs) have gained significant popularity due to the powerful capability to extract useful representations from graph data. As the need for efficient GNN comp…
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms
Ao Zhou, Jianlei Yang, Yingjie Qi +4
Graph neural networks (GNNs) have emerged as a popular strategy for handling non-Euclidean data due to their state-of-the-art performance. However, most of the current GNN model de…
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform
Mingjun Li, Jianlei Yang, Yingjie Qi +6
Event cameras are bio-inspired vision sensors that asynchronously represent pixel-level brightness changes as event streams. Event-based monocular multi-view stereo (EMVS) is a tec…
Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms
Ao Zhou, Jianlei Yang, Yeqi Gao +7
Graph neural networks (GNN) have achieved state-of-the-art performance on various industrial tasks. However, the poor efficiency of GNN inference and frequent Out-Of-Memory (OOM) p…
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture
Xueyan Wang, Jianlei Yang, Yinglin Zhao +7
Triangle counting (TC) is a fundamental problem in graph analysis and has found numerous applications, which motivates many TC acceleration solutions in the traditional computing p…