25 citations · 35 across the 8 of their papers we have counts for
8 papers
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method
Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili +2
Automatic synthesis of analog and Radio Frequency (RF) circuits is a trending approach that requires an efficient circuit modeling method. This is due to the expensive cost of runn…
MTrainS: Improving DLRM training efficiency using heterogeneous memories
Hiwot Tadese Kassa, Paul Johnson, Jason Akers +7
Recommendation models are very large, requiring terabytes (TB) of memory during training. In pursuit of better quality, the model size and complexity grow over time, which requires…
Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher
Yichen Yang, Jingtao Li, Nishil Talati +5
The irregular nature of memory accesses of graph workloads makes their performance poor on modern computing platforms. On manycore reconfigurable architectures (MRAs), in particula…
HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs
Aporva Amarnath, Subhankar Pal, Hiwot Kassa +6
Systems-on-Chips (SoCs) that power autonomous vehicles (AVs) must meet stringent performance and safety requirements prior to deployment. With increasing complexity in AV applicati…
F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption (Extended Version)
Axel Feldmann, Nikola Samardzic, Aleksandar Krastev +6
Fully Homomorphic Encryption (FHE) allows computing on encrypted data, enabling secure offloading of computation to untrusted serves. Though it provides ideal security, FHE is expe…
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
Sung Kim, Morteza Fayazi, Alhad Daftardar +10
We present Versa, an energy-efficient processor with 36 systolic ARM Cortex-M4F cores and a runtime-reconfigurable memory hierarchy. Versa exploits algorithm-specific characteristi…
Tablext: A Combined Neural Network And Heuristic Based Table Extractor
Zach Colter, Morteza Fayazi, Zineb Benameur-El +3
A significant portion of the data available today is found within tables. Therefore, it is necessary to use automated table extraction to obtain thorough results when data-mining.…
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors
Augusto Vega, Aporva Amarnath, John-David Wellman +6
The proliferation of heterogeneous chip multiprocessors in recent years has reached unprecedented levels. Traditional homogeneous platforms have shown fundamental limitations when…