3 papers
cs.AR2025
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
Zhuorui Zhao, Ruidi Qiu, Ing-Chao Lin +3
Large Language Models (LLMs) have demonstrated promising capabilities in generating Verilog code from module specifications. To improve the quality of such generated Verilog codes,…
cs.SE2024
CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design
Ruidi Qiu, Grace Li Zhang, Rolf Drechsler +2
Functional simulation is an essential step in digital hardware design. Recently, there has been a growing interest in leveraging Large Language Models (LLMs) for hardware testbench…
eess.SY2024
LLM-Aided Efficient Hardware Design Automation
Kangwei Xu, Ruidi Qiu, Zhuorui Zhao +3
With the rapidly increasing complexity of modern chips, hardware engineers are required to invest more effort in tasks such as circuit design, verification, and physical implementa…