47 citations · 110 across the 5 of their papers we have counts for
6 papers
SparseCol: A 1320 BTOPS/W Precision-scalable NPU Exploiting Training-free Structured Bit-level Sparsity and Dynamic Dataflow
Man Shi, Vikram Jain, Weijie Jiang +4
Bit-serial computation enables sequential processing of data at the bit level, providing several advantages, such as scalable computational precision. This approach has gained sign…
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration
Man Shi, Vikram Jain, Antony Joseph +2
Bit-serial computation facilitates bit-wise sequential data processing, offering numerous benefits, such as a reduced area footprint and dynamically-adaptive computational precisio…
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge
Vikram Jain, Matheus Cavalcante, Nazareno Bruschi +6
Emerging deep neural network (DNN) applications require high-performance multi-core hardware acceleration with large data bursts. Classical network-on-chips (NoCs) use serial packe…
TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge
Vikram Jain, Sebastian Giraldo, Jaro De Roose +3
Extreme edge devices or Internet-of-thing nodes require both ultra-low power always-on processing as well as the ability to do on-demand sampling and processing. Moreover, support…
CONVOLVE: Smart and seamless design of smart edge processors
M. Gomony, F. Putter, A. Gebregiorgis +25
With the rise of Deep Learning (DL), our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, rel…
ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework
Linyan Mei, Pouya Houshmand, Vikram Jain +2
Building efficient embedded deep learning systems requires a tight co-design between DNN algorithms, memory hierarchy, and dataflow. However, owing to the large degrees of freedom…