activity
20202025
collaborators

5 papers

cs.AR2025

A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro Using 2D-Weighted Capacitor Array for Complex Number Mac Operations

Shota Konno, Che-Kai Liu, Sigang Ryu +2

A 28nm dense 6T-SRAM Digital(D)/Analog(A) Hybrid compute-in-memory (CIM) macro supporting complex num-ber MAC operation is presented. By introducing a 2D-weighted Capacitor Array,…

cs.ET2025

Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory

Ying-Hao Wei, Zishen Wan, Brian Crafton +2

With the escalating demand for power-efficient neural network architectures, non-volatile compute-in-memory designs have garnered significant attention. However, owing to the natur…

cs.AR2024

H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations

Zishen Wan, Che-Kai Liu, Mohamed Ibrahim +4

Disentangling attributes of various sensory signals is central to human-like perception and reasoning and a critical task for higher-order cognitive and neuro-symbolic AI systems.…

cs.AR2020

Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics

Brian Crafton, Samuel Spetalnick, Gauthaman Murali +3

Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most data intensive applications. This has fou…

eess.SP2020

Counting Cards: Exploiting Variance and Data Distributions for Robust Compute In-Memory

Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury

Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most data intensive applications. This has fou…