59 citations · 89 across the 12 of their papers we have counts for
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cs.AR2021
Efficient Instruction Scheduling using Real-time Load Delay Tracking
Andreas Diavastos, Trevor E. Carlson
Many hardware structures in today's high-performance out-of-order processors do not scale in an efficient way. To address this, different solutions have been proposed that build ex…
cs.CR2021★ 8 cited
Leaking Control Flow Information via the Hardware Prefetcher
Yun Chen, Lingfeng Pei, Trevor E. Carlson
Modern processor designs use a variety of microarchitectural methods to achieve high performance. Unfortunately, new side-channels have often been uncovered that exploit these enha…
cs.CR2021
Mitigating Power Attacks through Fine-Grained Instruction Reordering
Yun Chen, Ali Hajiabadi, Romain Poussier +3
Side-channel attacks are a security exploit that take advantage of information leakage. They use measurement and analysis of physical parameters to reverse engineer and extract sec…