4 papers
VersaQ-3D: Architecture Support for Visual Geometry Grounded Transformers via Versatile Quantization
Yipu Zhang, Jintao Cheng, Xingyu Liu +8
The paper introduces VersaQ-3D, a co-designed quantization algorithm and reconfigurable accelerator that enables low‑bit (4‑bit) inference of Visual Geometry Grounded Transformers…
FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs
Jiawei Liang, Haotong Qin, Linfeng Du +7
Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable…
FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
Xingyu Liu, Jiawei Liang, Linfeng Du +5
In this work, we present FLEX, an FPGA-CPU accelerator for mixed-cell-height legalization tasks. We address challenges from the following perspectives. First, we optimize the task…
DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator
Xingyu Liu, Jiawei Liang, Yipu Zhang +5
We propose a hardware-efficient RBD accelerator based on FPGA, introducing three key innovations. First, we propose a precision-aware quantization framework that reduces DSP demand…