8 citations · 11 across the 2 of their papers we have counts for
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cs.AR2021★ 8 cited
MANA: Microarchitecting an Instruction Prefetcher
Ali Ansari, Fatemeh Golshan, Pejman Lotfi-Kamran +1
L1 instruction (L1-I) cache misses are a source of performance bottleneck. Sequential prefetchers are simple solutions to mitigate this problem; however, prior work has shown that…
cs.AR2020★ 3 cited
A Survey on Recent Hardware Data Prefetching Approaches with An Emphasis on Servers
Mohammad Bakhshalipour, Mehran Shakerinava, Fatemeh Golshan +3
Data prefetching, i.e., the act of predicting application's future memory accesses and fetching those that are not in the on-chip caches, is a well-known and widely-used approach t…