31 citations · 93 across the 8 of their papers we have counts for
5 papers · 1 filter
AP-DRL: A Synergistic Algorithm-Hardware Framework for Automatic Task Partitioning of Deep Reinforcement Learning on Versal ACAP
Enlai Li, Zhe Lin, Sharad Sinha +1
Deep reinforcement learning has demonstrated remarkable success across various domains. However, the tight coupling between training and inference processes makes accelerating DRL…
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors
Zhe Lin, Sharad Sinha, Hao Liang +2
Modern multicore systems are migrating from homogeneous systems to heterogeneous systems with accelerator-based computing in order to overcome the barriers of performance and power…
Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA
Zhe Lin, Wei Zhang, Sharad Sinha
Fine-grained runtime power management techniques could be promising solutions for power reduction. Therefore, it is essential to establish accurate power monitoring schemes to obta…
An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power
Zhe Lin, Sharad Sinha, Wei Zhang
As field-programmable gate arrays become prevalent in critical application domains, their power consumption is of high concern. In this paper, we present and evaluate a power monit…
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
Zhe Lin, Jieru Zhao, Sharad Sinha +1
High-level synthesis (HLS) enables designers to customize hardware designs efficiently. However, it is still challenging to foresee the correlation between power consumption and HL…