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cs.AR2025
ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors
Haoran Wu, Ce Guo, Wayne Luk +1
Bayesian Optimization (BO) has shown promise in tuning processor design parameters. However, standard BO does not support constraints involving categorical parameters such as types…
cs.AR2025
ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness
Ce Guo, Tong Zhao
Field-Programmable Gate Arrays (FPGAs) are widely used in modern hardware design, yet writing Hardware Description Language (HDL) code for FPGA implementation remains a complex and…
cs.AR2025
MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration
Zhiqiang Que, Jose G. F. Coutinho, Ce Guo +2
This paper presents a unified framework for codifying and automating optimization strategies to efficiently deploy deep neural networks (DNNs) on resource-constrained hardware, suc…