19 citations · 31 across the 8 of their papers we have counts for
8 papers
Mestra: Exploring Migration on Virtualized CGRAs
Agamemnon Kyriazis, Panagiotis Miliadis, Dimitris Theodoropoulos +2
As modern Coarse Grain Reconfigurable Arrays (CGRAs) grow in size, efficient utilization of the available fabric by a single application becomes increasingly difficult. Existing CG…
Evaluating the Effectiveness of Microarchitectural Hardware Fault Detection for Application-Specific Requirements
Konstantinos-Nikolaos Papadopoulos, Christina Giannoula, Nikolaos-Charalampos Papadopoulos +3
Reliability is necessary in safety-critical applications spanning numerous domains. Conventional hardware-based fault tolerance techniques, such as component redundancy, ensure rel…
Vitamin-V: Expanding Open-Source RISC-V Cloud Environments
Ramon Canal, Stefano Di Carlo, Dimitris Gizopoulos +12
Among the key contributions of Vitamin-V (2023-2025 Horizon Europe project), we develop a complete RISC-V open-source software stack for cloud services with comparable performance…
Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services
A. Arelakis, J. M. Arnau, J. L. Berral +20
Vitamin-V is a 2023-2025 Horizon Europe project that aims to develop a complete RISC-V open-source software stack for cloud services with comparable performance to the cloud-domina…
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining
C. Peltekis, D. Filippas, G. Dimitrakopoulos +2
Convolutional Neural Networks (CNNs) are the state-of-the-art solution for many deep learning applications. For maximum scalability, their computation should combine high performan…
Performance landscape of resource-constrained platforms targeting DNNs
Panagiotis Miliadis, Christos-Savvas Bouganis, Dionisios Pnevmatikatos
Over the recent years, a significant number of complex, deep neural networks have been developed for a variety of applications including speech and face recognition, computer visio…
Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator
Nikolaos Charalampos Papadopoulos, Vasileios Karakostas, Konstantinos Nikas +2
The Rocket Chip Generator uses a collection of parameterized processor components to produce RISC-V-based SoCs. It is a powerful tool that can produce a wide variety of processor d…
Design Guidelines for High-Performance SCM Hierarchies
Dmitrii Ustiugov, Alexandros Daglis, Javier Picorel +4
With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a few…