2 citations · 7 across the 14 of their papers we have counts for
15 papers
EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang +2
Design rule check (DRC) closure remains a major bottleneck in advanced-node physical design. Although detailed routers are rule-aware, residual design rule violations (DRVs) often…
GR-Evolve: Design-Adaptive Global Routing via LLM-Driven Algorithm Evolution
Taizun Jafri, Vidya A. Chhabria
Modern ASIC design is becoming increasingly complex, driving up design costs while limiting productivity gains from existing EDA tools. Despite decades of progress, current tools r…
DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Design
Bing-Yue Wu, Vidya A. Chhabria
Machine learning (ML) has demonstrated significant promise in various physical design (PD) tasks. However, model generalizability remains limited by the availability of high-qualit…
CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs
Jiajun Hu, Chetan Choppali Sudarshan, Vidya A. Chhabria +1
Over the years, the chip industry has consistently developed high-performance processors to address the increasing demands across diverse applications. However, the rapid expansion…
EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD
Bing-Yue Wu, Utsav Sharma, Sai Rahul Dhanvi Kankipati +5
Large language models (LLMs) serve as powerful tools for design, providing capabilities for both task automation and design assistance. Recent advancements have shown tremendous po…
IR-Aware ECO Timing Optimization Using Reinforcement Learning
Wenjing Jiang, Vidya A. Chhabria, Sachin S. Sapatnekar
Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analys…
GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions
Chetan Choppali Sudarshan, Aman Arora, Vidya A. Chhabria
Growing global concerns about climate change highlight the need for environmentally sustainable computing. The ecological impact of computing, including operational and embodied, i…
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
Chetan Choppali Sudarshan, Nikhil Matkar, Sarma Vrudhula +2
Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to an i…
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route
Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng +1
Due to the unavailability of routing information in design stages prior to detailed routing (DR), the tasks of timing prediction and optimization pose major challenges. Inaccurate…
A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects
Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
Electromigration (EM) is a key reliability issue in deeply scaled technology nodes. Traditional EM methods first filter immortal wires using the Blech criterion, and then perform E…
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu +3
Power delivery network (PDN) analysis and thermal analysis are computationally expensive tasks that are essential for successful IC design. Algorithmically, both these analyses hav…
OpeNPDN: A Neural-network-based Framework for Power Delivery Network Synthesis
Vidya A. Chhabria, Sachin S. Sapatnekar
Power delivery network (PDN) design is a nontrivial, time-intensive, and iterative task. Correct PDN design must account for considerations related to power bumps, currents, blocka…
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects
Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
Traditional methodologies for analyzing electromigration (EM) in VLSI circuits first filter immortal wires using Blech's criterion, and then perform detailed EM analysis on the rem…
MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification
Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren +3
Vectored IR drop analysis is a critical step in chip signoff that checks the power integrity of an on-chip power delivery network. Due to the prohibitive runtimes of dynamic IR dro…
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu +3
Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) ne…