1 citations · 1 across the 4 of their papers we have counts for
5 papers
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report
M. Guthaus, C. Batten, E. Brunvand +6
As the pace of progress that has followed Moore's law continues to diminish, it is critical that the US support Integrated Circuit (IC or chip) education and research to maintain t…
Quantifying the Efficacy of Logic Locking Methods
Joseph Sweeney, Deepali Garg, Lawrence Pileggi
The outsourced manufacturing of integrated circuits has increased the risk of intellectual property theft. In response, logic locking techniques have been developed for protecting…
Modeling Techniques for Logic Locking
Joseph Sweeney, Marijn J. H. Heule, Lawrence Pileggi
Logic locking is a method to prevent intellectual property (IP) piracy. However, under a reasonable attack model, SAT-based methods have proven to be powerful in obtaining the secr…
Securing Digital Systems via Split-Chip Obfuscation
Joseph Sweeney, Samuel Pagliarini, Lawrence Pileggi
Security is an important facet of integrated circuit design for many applications. IP privacy and Trojan insertion are growing threats as circuit fabrication in advanced nodes almo…
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Peng Li, Frank Liu, Xin Li +2
Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of paramet…