72 citations · 203 across the 31 of their papers we have counts for
33 papers
Invited: Toward Accurate, Large-scale Electromigration Analysis and Optimization in Integrated Systems
Sachin S. Sapatnekar
Electromigration, a significant lifetime reliability concern in highperformance integrated circuits, is projected to grow even more important in future heterogeneously integrated s…
Supporting Higher-Order Interactions in Practical Ising Machines
Nafisa Sadaf Prova, Hüsrev Cılasun, Abhimanyu Kumar +3
Ising machines as hardware solvers of combinatorial optimization problems (COPs) can efficiently explore large solution spaces due to their inherent parallelism and physics-based d…
DROID: Discrete-Time Simulation for Ring-Oscillator-Based Ising Design
Abhimanyu Kumar, Ramprasath S., Chris H. Kim +2
Many combinatorial problems can be mapped to Ising machines, i.e., networks of coupled oscillators that settle to a minimum-energy ground state, from which the problem solution is…
Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables
Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap +2
Device sizing is crucial for meeting performance specifications in operational transconductance amplifiers (OTAs), and this work proposes an automated sizing framework based on a t…
HETRI: Heterogeneous Ising Multiprocessing
Ahmet Efe, Hüsrev Cılasun, Abhimanyu Kumar +4
Ising machines are effective solvers for complex combinatorial optimization problems. The idea is mapping the optimal solution(s) to a combinatorial optimization problem to the min…
IR-Aware ECO Timing Optimization Using Reinforcement Learning
Wenjing Jiang, Vidya A. Chhabria, Sachin S. Sapatnekar
Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analys…
Experimental demonstration of magnetic tunnel junction-based computational random-access memory
Yang Lv, Brandon R. Zink, Robert P. Bloom +9
Conventional computing paradigm struggles to fulfill the rapidly growing demands from emerging applications, especially those for machine intelligence, because much of the power an…
3SAT on an All-to-All-Connected CMOS Ising Solver Chip
Hüsrev Cılasun, Ziqing Zeng, Ramprasath S +6
This work solves 3SAT, a classical NP-complete problem, on a CMOS-based Ising hardware chip with all-to-all connectivity. The paper addresses practical issues in going from algorit…
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators
Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng +8
Parameterizable machine learning (ML) accelerators are the product of recent breakthroughs in ML. To fully enable their design space exploration (DSE), we propose a physical-design…
Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations
Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng +4
Today's performance analysis frameworks for deep learning accelerators suffer from two significant limitations. First, although modern convolutional neural network (CNNs) consist o…
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
Chetan Choppali Sudarshan, Nikhil Matkar, Sarma Vrudhula +2
Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to an i…
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route
Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng +1
Due to the unavailability of routing information in design stages prior to detailed routing (DR), the tasks of timing prediction and optimization pose major challenges. Inaccurate…
On Error Correction for Nonvolatile Processing-In-Memory
Hüsrev Cılasun, Salonik Resch, Zamshed I. Chowdhury +6
Processing in memory (PiM) represents a promising computing paradigm to enhance performance of numerous data-intensive applications. Variants performing computing directly in emerg…
A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects
Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
Electromigration (EM) is a key reliability issue in deeply scaled technology nodes. Traditional EM methods first filter immortal wires using the Blech criterion, and then perform E…
Towards Homomorphic Inference Beyond the Edge
Salonik Resch, Zamshed I. Chowdhury, Husrev Cilasun +5
Beyond edge devices can function off the power grid and without batteries, enabling them to operate in difficult to access regions. However, energy costly long-distance communicati…
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu +3
Power delivery network (PDN) analysis and thermal analysis are computationally expensive tasks that are essential for successful IC design. Algorithmically, both these analyses hav…
OpeNPDN: A Neural-network-based Framework for Power Delivery Network Synthesis
Vidya A. Chhabria, Sachin S. Sapatnekar
Power delivery network (PDN) design is a nontrivial, time-intensive, and iterative task. Correct PDN design must account for considerations related to power bumps, currents, blocka…
Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator
Masoud Zabihi, Salonik Resch, Husrev Cılasun +5
This paper describes how 3D XPoint memory arrays can be used as in-memory computing accelerators. We first show that thresholded matrix-vector multiplication (TMVM), the fundamenta…
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects
Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
Traditional methodologies for analyzing electromigration (EM) in VLSI circuits first filter immortal wires using Blech's criterion, and then perform detailed EM analysis on the rem…
GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching
Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal +2
Graph neural networks (GNN) analysis engines are vital for real-world problems that use large graph models. Challenges for a GNN hardware platform include the ability to (a) host a…
MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification
Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren +3
Vectored IR drop analysis is a critical step in chip signoff that checks the power integrity of an on-chip power delivery network. Due to the prohibitive runtimes of dynamic IR dro…
A general approach for identifying hierarchical symmetry constraints for analog circuit layout
Kishor Kunal, Jitesh Poojary, Tonmoy Dhar +3
Analog layout synthesis requires some elements in the circuit netlist to be matched and placed symmetrically. However, the set of symmetries is very circuit-specific and a versatil…
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu +3
Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) ne…
ALIGN: A System for Automating Analog Layout
Tonmoy Dhar, Kishor Kunal, Yaguang Li +11
ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an…