26 citations · 48 across the 12 of their papers we have counts for
6 papers · 1 filter
Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA
Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson +3
The challenges associated with effectively programming FPGAs have been a major blocker in popularising reconfigurable architectures for HPC workloads. However new compiler technolo…
Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang
Nick Brown, Maurice Jamieson, Anton Lydike +2
MLIR has become popular since it was open sourced in 2019. A sub-project of LLVM, the flexibility provided by MLIR to represent Intermediate Representations (IR) as dialects at dif…
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU
Nick Brown, Maurice Jamieson, Joseph Lee +1
The Sophon SG2042 is the world's first commodity 64-core RISC-V CPU for high performance workloads and an important question is whether the SG2042 has the potential to encourage th…
Experiences of running an HPC RISC-V testbed
Nick Brown, Maurice Jamieson, Joseph K. L. Lee
Funded by the UK ExCALIBUR H\&ES exascale programme, in early 2022 a RISC-V testbed for HPC was stood up to provide free access for scientific software developers to experiment wit…
Backporting RISC-V Vector assembly
Joseph K. L. Lee, Maurice Jamieson, Nick Brown
Leveraging vectorisation, the ability for a CPU to apply operations to multiple elements of data concurrently, is critical for high performance workloads. However, at the time of w…
Test-driving RISC-V Vector hardware for HPC
Joseph K. L. Lee, Maurice Jamieson, Nick Brown +1
Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisatio…