26 citations · 48 across the 12 of their papers we have counts for
11 papers · 1 filter
Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC
Nick Brown, Maurice Jamieson
Whilst RISC-V has grown phenomenally quickly in embedded computing, it is yet to gain significant traction in High Performance Computing (HPC). However, as we move further into the…
A shared compilation stack for distributed-memory parallelism in stencil DSLs
George Bisbas, Anton Lydike, Emilien Bauer +8
Domain Specific Languages (DSLs) increase programmer productivity and provide high performance. Their targeted abstractions allow scientists to express problems at a high level, pr…
Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA
Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson +3
The challenges associated with effectively programming FPGAs have been a major blocker in popularising reconfigurable architectures for HPC workloads. However new compiler technolo…
Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang
Nick Brown, Maurice Jamieson, Anton Lydike +2
MLIR has become popular since it was open sourced in 2019. A sub-project of LLVM, the flexibility provided by MLIR to represent Intermediate Representations (IR) as dialects at dif…
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU
Nick Brown, Maurice Jamieson, Joseph Lee +1
The Sophon SG2042 is the world's first commodity 64-core RISC-V CPU for high performance workloads and an important question is whether the SG2042 has the potential to encourage th…
Experiences of running an HPC RISC-V testbed
Nick Brown, Maurice Jamieson, Joseph K. L. Lee
Funded by the UK ExCALIBUR H\&ES exascale programme, in early 2022 a RISC-V testbed for HPC was stood up to provide free access for scientific software developers to experiment wit…
Backporting RISC-V Vector assembly
Joseph K. L. Lee, Maurice Jamieson, Nick Brown
Leveraging vectorisation, the ability for a CPU to apply operations to multiple elements of data concurrently, is critical for high performance workloads. However, at the time of w…
Test-driving RISC-V Vector hardware for HPC
Joseph K. L. Lee, Maurice Jamieson, Nick Brown +1
Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisatio…
Performance of the Vipera framework for DSLs on micro-core architectures
Maurice Jamieson, Nick Brown
Vipera provides a compiler and runtime framework for implementing dynamic Domain-Specific Languages on micro-core architectures. The performance and code size of the generated code…
Benchmarking micro-core architectures for detecting disasters at the edge
Maurice Jamieson, Nick Brown
Leveraging real-time data to detect disasters such as wildfires, extreme weather, earthquakes, tsunamis, human health emergencies, or global diseases is an important opportunity. H…
High level programming abstractions for leveraging hierarchical memories with micro-core architectures
Maurice Jamieson, Nick Brown
Micro-core architectures combine many low memory, low power computing cores together in a single package. These are attractive for use as accelerators but due to limited on-chip me…