2 citations · 4 across the 3 of their papers we have counts for
5 papers · 1 filter
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory
Nika Mansouri Ghiasi, Mohammad Sadrosadati, Geraldo F. Oliveira +9
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between la…
SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM
Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio +7
Processing-using-DRAM has been proposed for a limited set of basic operations (i.e., logic operations, addition). However, in order to enable full adoption of processing-using-DRAM…
pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables
João Dinis Ferreira, Gabriel Falcao, Juan Gómez-Luna +8
Data movement between the main memory and the processor is a key contributor to execution time and energy consumption in memory-intensive applications. This data movement bottlenec…
SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM
Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio +7
Processing-using-DRAM has been proposed for a limited set of basic operations (i.e., logic operations, addition). However, in order to enable the full adoption of processing-using-…
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders
Leonid Yavits, Lois Orosa, Suyash Mahar +4
Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory fa…