3 citations · 8 across the 7 of their papers we have counts for
7 papers
The Hitchhiker's Guide to Programming and Optimizing Cache Coherent Heterogeneous Systems: CXL, NVLink-C2C, and AMD Infinity Fabric
Zixuan Wang, Suyash Mahar, Luyi Li +9
We present a thorough analysis of the use of modern heterogeneous systems interconnected by various cachecoherent links, including CXL, NVLink-C2C, and Infinity Fabric. We studied…
Telepathic Datacenters: Fast RPCs using Shared CXL Memory
Suyash Mahar, Ehsan Hajyjasini, Seungjin Lee +3
Datacenter applications often rely on remote procedure calls (RPCs) for fast, efficient, and secure communication. However, RPCs are slow, inefficient, and hard to use as they requ…
CXL Shared Memory Programming: Barely Distributed and Almost Persistent
Yi Xu, Suyash Mahar, Ziheng Liu +2
While Compute Express Link (CXL) enables support for cache-coherent shared memory among multiple nodes, it also introduces new types of failures--processes can fail before data doe…
Snapshot: Fast, Userspace Crash Consistency for CXL and PM Using msync
Suyash Mahar, Mingyao Shen, Terence Kelly +1
Crash consistency using persistent memory programming libraries requires programmers to use complex transactions and manual annotations. In contrast, the failure-atomic msync() (FA…
Puddles: Application-Independent Recovery and Location-Independent Data for Persistent Memory
Suyash Mahar, Mingyao Shen, TJ Smith +2
In this paper, we argue that current work has failed to provide a comprehensive and maintainable in-memory representation for persistent memory. PM data should be easily mappable i…
Workload Behavior Driven Memory Subsystem Design for Hyperscale
Suyash Mahar, Hao Wang, Wei Shu +1
Hyperscalars run services across a large fleet of servers, serving billions of users worldwide. These services, however, behave differently than commonly available benchmark suites…
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders
Leonid Yavits, Lois Orosa, Suyash Mahar +4
Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory fa…