124 citations · 433 across the 23 of their papers we have counts for
19 papers · 1 filter
ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems
Nika Mansouri Ghiasi, Nandita Vijaykumar, Geraldo F. Oliveira +7
Partitioning applications between NDP and host CPU cores causes inter-segment data movement overhead, which is caused by moving data generated from one segment (e.g., instructions,…
NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators
Aditya Manglik, Minesh Patel, Haiyu Mao +4
Resistive Random-Access Memory (RRAM) is well-suited to accelerate neural network (NN) workloads as RRAM-based Processing-in-Memory (PIM) architectures natively support highly-para…
DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
Ataberk Olgun, Hasan Hassan, A. Giray Yağlıkçı +6
To understand and improve DRAM performance, reliability, security and energy efficiency, prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art…
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
Abdullah Giray Yağlıkçı, Ataberk Olgun, Minesh Patel +5
DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interferi…
Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices
A. Giray Yağlıkçı, Haocong Luo, Geraldo F. de Oliviera +7
RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and precharging a DRAM row, and thus alternating the voltage of a row's wordline between low and high v…
DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
F. Nisa Bostancı, Ataberk Olgun, Lois Orosa +5
Random number generation is an important task in a wide variety of critical applications including cryptographic algorithms, scientific simulations, and industrial testing tools. T…
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
Lois Orosa, Yaohua Wang, Mohammad Sadrosadati +10
DRAM is the dominant main memory technology used in modern computing systems. Computing systems implement a memory controller that interfaces with DRAM via DRAM commands. DRAM exec…
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
Geraldo F. Oliveira, Juan Gómez-Luna, Lois Orosa +5
Data movement between the CPU and main memory is a first-order obstacle against improving performance, scalability, and energy efficiency in modern systems. Computer systems employ…
pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables
João Dinis Ferreira, Gabriel Falcao, Juan Gómez-Luna +8
Data movement between the main memory and the processor is a key contributor to execution time and energy consumption in memory-intensive applications. This data movement bottlenec…
Reducing Solid-State Drive Read Latency by Optimizing Read-Retry
Jisung Park, Myungsuk Kim, Myoungjun Chun +3
3D NAND flash memory with advanced multi-level cell techniques provides high storage density, but suffers from significant performance degradation due to a large number of read-ret…
SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures
Christina Giannoula, Nandita Vijaykumar, Nikela Papadopoulou +7
Near-Data-Processing (NDP) architectures present a promising way to alleviate data movement costs and can provide significant performance and energy benefits to parallel applicatio…
Reducing Solid-State Drive Read Latency by Optimizing Read-Retry (Extended Abstract)
Jisung Park, Myungsuk Kim, Myoungjun Chun +3
3D NAND flash memory with advanced multi-level cell techniques provides high storage density, but suffers from significant performance degradation due to a large number of read-ret…
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders
Leonid Yavits, Lois Orosa, Suyash Mahar +4
Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory fa…
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors
Jawad Haj-Yahya, Mohammed Alser, Jeremie S. Kim +5
Modern client processors typically use one of three commonly-used power delivery network (PDN): 1) motherboard voltage regulators (MBVR), 2) integrated voltage regulators (IVR), an…
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
Yaohua Wang, Lois Orosa, Xiangjun Peng +8
DRAM Main memory is a performance bottleneck for many applications due to the high access latency. In-DRAM caches work to mitigate this latency by augmenting regular-latency DRAM w…
Optically Connected Memory for Disaggregated Data Centers
Jorge Gonzalez, Alexander Gazman, Maarten Hattink +8
Recent advances in integrated photonics enable the implementation of reconfigurable, high-bandwidth, and low energy-per-bit interconnects in next-generation data centers. We propos…
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci +4
In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chi…
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
Haocong Luo, Taha Shahroodi, Hasan Hassan +5
DRAM is the prevalent main memory technology, but its long access latency can limit the performance of many workloads. Although prior works provide DRAM designs that reduce DRAM ac…
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
Jeremie S. Kim, Minesh Patel, Hasan Hassan +2
We propose a new DRAM-based true random number generator (TRNG) that leverages DRAM cells as an entropy source. The key idea is to intentionally violate the DRAM access timing para…