2 papers
cs.AR2025
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Jason Blocklove, Shailja Thakur, Benjamin Tan +3
Traditionally, digital hardware designs are written in the Verilog hardware description language (HDL) and debugged manually by engineers. This can be time-consuming and error-pron…
cs.CR2025
Toward Automated Potential Primary Asset Identification in Verilog Designs
Subroto Kumer Deb Nath, Benjamin Tan
With greater design complexity, the challenge to anticipate and mitigate security issues provides more responsibility for the designer. As hardware provides the foundation of a sec…