From the 1 of 6 linked papers with an AI index.
5 citations · 5 across the 3 of their papers we have counts for
6 papers
The Road Less Traveled: Congestion-Aware NoC Placement and Packet Routing for FPGAs
Soheil Gholami Shahrouz, Vaughn Betz
To help scale to ever-larger and more complex designs, recent FPGA architectures now integrate network-on-chips (NoCs). NoCs help transfer high-bandwidth data over long distances w…
Jack of All Scales: A Versatile FPGA Tensor Block for MXFP Precisions
Marwan Mekhemer, Ahmed Elsousy, Balaji Venkatesh +4
The paper analyzes how current FPGA DSP blocks handle low‑precision microscaling floating‑point (MXFP) formats and proposes modest architectural changes to the DSP tensor mode so t…
Modeling, Optimizing and Exploring Multi-Die FPGA Routing Architectures
Amirhossein Poolad, Soheil Gholami Shahrouz, Andrew Boutros +1
Die stacking has enabled 2.5D FPGAs by integrating multiple active dice on a passive silicon interposer for improved yield and capacity, and paved the way for 3D architectures that…
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
Junius Pun, Xilai Dai, Grace Zgheib +4
Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices. For instance, FPGAs can efficiently implement ar…
H2PIPE: High throughput CNN Inference on FPGAs with High-Bandwidth Memory
Mario Doumet, Marius Stan, Mathew Hall +1
Convolutional Neural Networks (CNNs) combine large amounts of parallelizable computation with frequent memory access. Field Programmable Gate Arrays (FPGAs) can achieve low latency…
Field-Programmable Gate Array Architecture for Deep Learning: Survey & Future Directions
Andrew Boutros, Aman Arora, Vaughn Betz
Deep learning (DL) is becoming the cornerstone of numerous applications both in datacenters and at the edge. Specialized hardware is often necessary to meet the performance require…