2 papers
cond-mat.mes-hall2025
Design Optimization of Flip FET Standard Cells with Dual-sided Pins for Ultimate Scaling
Rui Gui, Haoran Lu, Jiacheng Sun +7
Recently, we proposed a novel transistor architecture for 3D stacked FETs called Flip FET (FFET), featuring N/P transistors back-to-back stacked and dual-sided interconnects. With…
physics.app-ph2025
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals
Haoran Lu, Xun Jiang, Yanbang Chu +7
As the conventional scaling of logic devices comes to an end, functional wafer backside and 3D transistor stacking are consensus for next-generation logic technology, offering cons…