11 papers
Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation
Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras +7
Valinor is a hardware‑OS cooperative substrate that provides a programmable allocation engine to accelerate physical memory allocation, achieving hardware‑level speed while retaini…
Revelator: Rapid Data Fetching via System-Software-Guided Hash-based Speculative Address Translation
Konstantinos Kanellopoulos, Konstantinos Sgouras, Harsh Songara +7
Address translation is a major performance bottleneck in modern computing systems. Predicting the physical address (PA) of requested data before address translation completes can h…
ColumnKeeper: Efficient Solutions to the ColumnDisturb Vulnerability in DRAM-based Systems
Andreas Kosmas Kakolyris, F. Nisa Bostanci, Ataberk Olgun +7
Modern DRAM chips are vulnerable to read disturbance phenomena such as RowHammer and RowPress, which induce bitflips after accessing nearby rows a certain number of times (the read…
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran +4
Long-latency load requests continue to limit the performance of high-performance processors. To increase the latency tolerance of a processor, architects have primarily relied on t…
HE-PIM: Demystifying Homomorphic Operations on a Real-world Processing-in-Memory System
Harshita Gupta, Mayank Kabra, Jaewoo Park +9
Homomorphic encryption (HE) enables computation over encrypted data, offering strong privacy guarantees for untrusted computing environments. Practical adoption remains limited by…
Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning
Rahul Bera, Zhenrong Lang, Caroline Hengartner +4
Prefetching and off-chip prediction are two techniques proposed to hide long memory access latencies in high-performance processors. In this work, we demonstrate that: (1) prefetch…