3 papers
cs.AR2025
Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization
Fenghua Wu, Evan Pan, Rahul Kande +5
SystemVerilog Assertions (SVAs) play a critical role in detecting and debugging functional bugs in digital chip design. However, generating SVAs has traditionally been a manual, la…
cs.CR2024
Fuzzerfly Effect: Hardware Fuzzing for Memory Safety
Mohamadreza Rostami, Chen Chen, Rahul Kande +3
Hardware-level memory vulnerabilities severely threaten computing systems. However, hardware patching is inefficient or difficult postfabrication. We investigate the effectiveness…
cs.CR2024
Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection
Mohamadreza Rostami, Shaza Zeitouni, Rahul Kande +5
Microarchitectural attacks represent a challenging and persistent threat to modern processors, exploiting inherent design vulnerabilities in processors to leak sensitive informatio…