10 citations · 36 across the 14 of their papers we have counts for
14 papers
Evaluating Architectural Trade-offs in CGRAs: The Impact of Scratchpad Memory and Heterogeneity on Compute-Intensive Kernels
María José Belda, Lara Orlandic, Fernando Castro +3
Modern edge computing applications, particularly high-throughput stream processing like Vision Transformers (ViTs), demand massive spatial parallelism and efficient data movement u…
A comprehensive evaluation of spatial co-execution on GPUs using MPS and MIG technologies
Jorge Villarrubia, Luis Costero, Francisco D. Igual +1
To mitigate the increasingly common underutilization of computational resources in modern GPUs, spatial sharing methods enable multiple applications to use them simultaneously. Thi…
Exposing Embedded Matrix Multiplication with polyhedral transformations for CGRA compilation
Yuxuan Wang, María José Belda, Fernando Castro +3
Matrix-matrix multiplication (mmul) is a dominant computing pattern in edge workloads, but in real applications it is often embedded within larger affine programs and intertwined w…
Leveraging Multi-Instance GPUs through moldable task scheduling
Jorge Villarrubia, Luis Costero, Francisco D. Igual +1
NVIDIA MIG (Multi-Instance GPU) allows partitioning a physical GPU into multiple logical instances with fully-isolated resources, which can be dynamically reconfigured. This work h…
Balanced segmentation of CNNs for multi-TPU inference
Jorge Villarrubia, Luis Costero, Francisco D. Igual +1
In this paper, we propose different alternatives for convolutional neural networks (CNNs) segmentation, addressing inference processes on computing architectures composed by multip…
Improving inference time in multi-TPU systems with profiled model segmentation
Jorge Villarrubia, Luis Costero, Francisco D. Igual +1
In this paper, we systematically evaluate the inference performance of the Edge TPU by Google for neural networks with different characteristics. Specifically, we determine that, g…
Teaching Experiences using the RVfpga Package
D. Chaver, S. Harris, L. Pinuel +13
The RVfpga course offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-w…
Advanced simulation-based predictive modelling for solar irradiance sensor farms
José L. Risco-Martín, Ignacio-Iker Prado-Rujas, Javier Campoy +2
As solar power continues to grow and replace traditional energy sources, the need for reliable forecasting models becomes increasingly important to ensure the stability and efficie…
Energy efficiency optimization of task-parallel codes on asymmetric architectures
Luis Costero, Francisco D. Igual, Katzalin Olcoz +1
We present a family of policies that, integrated within a runtime task scheduler (Nanox), pursue the goal of improving the energy efficiency of task-parallel executions with no int…
Leveraging knowledge-as-a-service (KaaS) for QoS-aware resource management in multi-user video transcoding
Luis Costero, Francisco D. Igual, Katzalin Olcoz +1
The coexistence of parallel applications in shared computing nodes, each one featuring different Quality of Service (QoS) requirements, carries out new challenges to improve resour…
Optimization of a Line Detection Algorithm for Autonomous Vehicles on a RISC-V with Accelerator
María José Belda, Katzalin Olcoz, Fernando Castro +1
In recent years, autonomous vehicles have attracted the attention of many research groups, both in academia and business, including researchers from leading companies such as Googl…
A Unified Cloud-Enabled Discrete Event Parallel and Distributed Simulation Architecture
José L. Risco-Martín, Kevin Henares, Saurabh Mittal +2
Cloud simulation environments today are largely employed to model and simulate complex systems for remote accessibility and variable capacity requirements. In this regard, scalabil…
Detecting time-fragmented cache attacks against AES using Performance Monitoring Counters
Iván Prada, Francisco D. Igual, Katzalin Olcoz
Cache timing attacks use shared caches in multi-core processors as side channels to extract information from victim processes. These attacks are particularly dangerous in cloud inf…
Revisiting Conventional Task Schedulers to Exploit Asymmetry in ARM big.LITTLE Architectures for Dense Linear Algebra
Luis Costero, Francisco D. Igual, Katzalin Olcoz +1
Dealing with asymmetry in the architecture opens a plethora of questions from the perspective of scheduling task-parallel applications, and there exist early attempts to address th…