31 citations · 70 across the 6 of their papers we have counts for
6 papers
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System
Zhe Lin, Sharad Sinha, Wei Zhang
Decision trees are machine learning models commonly used in various application scenarios. In the era of big data, traditional decision tree induction algorithms are not suitable f…
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors
Zhe Lin, Sharad Sinha, Hao Liang +2
Modern multicore systems are migrating from homogeneous systems to heterogeneous systems with accelerator-based computing in order to overcome the barriers of performance and power…
An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power
Zhe Lin, Sharad Sinha, Wei Zhang
As field-programmable gate arrays become prevalent in critical application domains, their power consumption is of high concern. In this paper, we present and evaluate a power monit…
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
Zhe Lin, Jieru Zhao, Sharad Sinha +1
High-level synthesis (HLS) enables designers to customize hardware designs efficiently. However, it is still challenging to foresee the correlation between power consumption and HL…
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Jieru Zhao, Tingyuan Liang, Liang Feng +4
Fast and accurate depth estimation, or stereo matching, is essential in embedded stereo vision systems, requiring substantial design effort to achieve an appropriate balance among…
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Jieru Zhao, Tingyuan Liang, Sharad Sinha +1
High-level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction level. Optimization of complex appl…