11 citations · 16 across the 7 of their papers we have counts for
7 papers
DAPO: Design Structure-Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning
Jinming Ge, Linfeng Du, Likith Anaparty +8
High-Level Synthesis (HLS) tools are widely adopted in FPGA-based domain-specific accelerator design. However, existing tools rely on fixed optimization strategies inherited from s…
Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration
Hanwei Fan, Ya Wang, Sicheng Li +2
With the continuous advancement of processors, modern micro-architecture designs have become increasingly complex. The vast design space presents significant challenges for human d…
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
Linfeng Du, Tingyuan Liang, Sharad Sinha +2
Multi-die FPGAs are widely adopted to deploy large hardware accelerators. Two factors impede the performance optimization of HLS designs implemented on multi-die FPGAs. On the one…
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA
Tingyuan Liang, Gengjie Chen, Jieru Zhao +2
On modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable mac…
AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
Tingyuan Liang, Jingsong Chen, Lei Li +1
Custom standard cell libraries can improve the final quality of the corresponding VLSI designs but properly customizing standard cell libraries remains challenging due to the compl…
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Jieru Zhao, Tingyuan Liang, Liang Feng +4
Fast and accurate depth estimation, or stereo matching, is essential in embedded stereo vision systems, requiring substantial design effort to achieve an appropriate balance among…
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Jieru Zhao, Tingyuan Liang, Sharad Sinha +1
High-level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction level. Optimization of complex appl…