2.5k citations · 2.6k across the 9 of their papers we have counts for
9 papers
Low-Energy Line Codes for On-Chip Networks
Beyza Dabak, Major Glenn, Jingyang Liu +5
Energy is a primary constraint in processor design, and much of that energy is consumed in on-chip communication. Communication can be intra-core (e.g., from a register file to an…
Spatially-Coupled QLDPC Codes
Siyi Yang, Robert Calderbank
Spatially-coupled (SC) codes is a class of convolutional LDPC codes that has been well investigated in classical coding theory thanks to their high performance and compatibility wi…
Topology-Aware Cooperative Data Protection in Blockchain-Based Decentralized Storage Networks
Siyi Yang, Ahmed Hareedy, Robert Calderbank +1
From currency to cloud storage systems, the continuous rise of the blockchain technology is moving various information systems towards decentralization. Blockchain-based decentrali…
Asymmetric LOCO Codes: Constrained Codes for Flash Memories
Ahmed Hareedy, Robert Calderbank
In data storage and data transmission, certain patterns are more likely to be subject to error when written (transmitted) onto the media. In magnetic recording systems with binary…
Hierarchical Coding to Enable Scalability and Flexibility in Heterogeneous Cloud Storage
Siyi Yang, Ahmed Hareedy, Robert Calderbank +1
In order to accommodate the ever-growing data from various, possibly independent, sources and the dynamic nature of data usage rates in practical applications, modern cloud data st…
Minimizing the Number of Detrimental Objects in Multi-Dimensional Graph-Based Codes
Ahmed Hareedy, Rohith Kuditipudi, Robert Calderbank
In order to meet the demands of data-hungry applications, data storage devices are required to be increasingly denser. Various sources of error appear with this increase in density…
LOCO Codes: Lexicographically-Ordered Constrained Codes
Ahmed Hareedy, Robert Calderbank
Line codes make it possible to mitigate interference, to prevent short pulses, and to generate streams of bipolar signals with no direct-current (DC) power content through balancin…
Correcting Two Deletions and Insertions in Racetrack Memory
Alireza Vahid, Georgios Mappouras, Daniel J. Sorin +1
Racetrack memory is a non-volatile memory engineered to provide both high density and low latency, that is subject to synchronization or shift errors. This paper describes a fast c…
Good Quantum Error-Correcting Codes Exist
A. R. Calderbank, Peter W. Shor
A quantum error-correcting code is defined to be a unitary mapping (encoding) of k qubits (2-state quantum systems) into a subspace of the quantum state space of n qubits such that…