29 citations · 29 across the 12 of their papers we have counts for
3 papers · 1 filter
LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification
Karthik Maddala, Bhabesh Mali, Chandan Karfa
Writing SystemVerilog Assertions (SVA) is an important but complex step in verifying Register Transfer Level (RTL) designs. Conventionally, experts need to understand the design sp…
MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs
Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa
The design and synthesis of masked cryptographic hardware implementations that are secure against power side-channel attacks (PSCAs) in the presence of glitches is a challenging ta…
ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation
Bhabesh Mali, Karthik Maddala, Vatsal Gupta +3
System Verilog Assertion (SVA) formulation -- a critical yet complex task is a prerequisite in the Assertion Based Verification (ABV) process. Traditionally, SVA formulation involv…