8 citations · 8 across the 7 of their papers we have counts for
7 papers
Modeling Task Mapping for Data-intensive Applications in Heterogeneous Systems
Martin Wilhelm, Hanna Geppert, Anna Drewes +1
We introduce a new model for the task mapping problem to aid in the systematic design of algorithms for heterogeneous systems including, but not limited to, CPUs, GPUs and FPGAs. A…
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu +4
The everlasting demand for higher computing power for deep neural networks (DNNs) drives the development of parallel computing architectures. 3D integration, in which chips are int…
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar +4
We introduce ratatoskr, an open-source framework for in-depth power, performance and area (PPA) analysis in NoCs for 3D-integrated and heterogeneous System-on-Chips (SoCs). It cove…
System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips
Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg +2
For a system-level design of Networks-on-Chip for 3D heterogeneous System-on-Chip (SoC), the locations of components, routers and vertical links are determined from an application…
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures
Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel +4
Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip. A special characteristic of communication n…
Simulation Environment for Link Energy Estimation in Networks-on-Chip with Virtual Channels
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar +3
Network-on-chip (NoC) is the most promising design paradigm for the interconnect architecture of a multiprocessor system-on-chip (MPSoC). On the downside, a NoC has a significant i…