32 citations · 55 across the 14 of their papers we have counts for
14 papers
Scalable Packed Layouts for Vector-Length-Agnostic ML Code Generation
Ege Beysel, Maximilian Bartel, Jan Moritz Joseph
Scalable vector instruction sets such as Arm SVE enable vector-length-agnostic (VLA) execution, allowing a single implementation to adapt across hardware with different vector leng…
parti-gem5: gem5's Timing Mode Parallelised
José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller +2
Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in m…
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Felix Staudigl, Thorben Fetz, Rebecca Pelke +4
Logic-in-memory (LIM) describes the execution of logic gates within memristive crossbar structures, promising to improve performance and energy efficiency. Utilizing only binary va…
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool
Nils Bosbach, Lukas Jünger, Jan Moritz Joseph +1
The increasing complexity of systems-on-a-chip requires the continuous development of electronic design automation tools. Nowadays, the simulation of systems-on-a-chip using virtua…
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs
Yee Yang Tan, Felix Staudigl, Lukas Jünger +3
Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling compared to slow si…
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation
Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel +5
Memristor-based crossbar arrays represent a promising emerging memory technology to replace conventional memories by offering a high density and enabling computing-in-memory (CIM)…