55 citations · 105 across the 5 of their papers we have counts for
5 papers
Application-Level Validation of Accelerator Designs Using a Formal Software/Hardware Interface
Bo-Yuan Huang, Steven Lyubomirsky, Yi Li +10
Ideally, accelerator development should be as easy as software development. Several recent design languages/tools are working toward this goal, but actually testing early designs o…
Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration (long version)
Pareesa Ameneh Golnari, Sharad Malik
Accelerators for sparse matrix multiplication are important components in emerging systems. In this paper, we study the main challenges of accelerating Sparse Matrix Multiplication…
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification
Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan +3
Modern Systems-on-Chip (SoC) designs are increasingly heterogeneous and contain specialized semi-programmable accelerators in addition to programmable processors. In contrast to th…
Constrained Sampling and Counting: Universal Hashing Meets SAT Solving
Kuldeep S. Meel, Moshe Vardi, Supratik Chakraborty +5
Constrained sampling and counting are two fundamental problems in artificial intelligence with a diverse range of applications, spanning probabilistic reasoning and planning to con…
Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom
Divjyot Sethi, Muralidhar Talupur, Sharad Malik
We consider the problem of verifying deadlock freedom for symmetric cache coherence protocols. In particular, we focus on a specific form of deadlock which is useful for the cache…