activity
20182021
most citedPowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

91 citations · 325 across the 11 of their papers we have counts for

collaborators

15 papers

cs.LG20216 cited

Privacy-Preserving Representation Learning on Graphs: A Mutual Information Perspective

Binghui Wang, Jiayi Guo, Ang Li +2

Learning with graphs has attracted significant attention recently. Existing representation learning methods on graphs have achieved state-of-the-art performance on various graph-re…

cs.LG20209 cited

Provable Defense against Privacy Leakage in Federated Learning from Representation Perspective

Jingwei Sun, Ang Li, Binghui Wang +3

Federated learning (FL) is a popular distributed learning framework that can reduce privacy risks by not explicitly sharing private data. However, recent works demonstrated that sh…

cs.LG20206 cited

Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation

Zhiyao Xie, Rongjian Liang, Xiaoqing Xu +3

Net length is a key proxy metric for optimizing timing and power across various stages of a standard digital design flow. However, the bulk of net length information is not availab…

cs.LG202091 cited

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

Zhiyao Xie, Haoxing Ren, Brucek Khailany +4

IR drop is a fundamental constraint required by almost all chip designs. However, its evaluation usually takes a long time that hinders mitigation techniques for fixing its violati…

cs.LG202053 cited

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning

Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang +7

Design flow parameters are of utmost importance to chip design quality and require a painfully long time to evaluate their effects. In reality, flow parameter tuning is usually per…

cs.LG2020

Fast IR Drop Estimation with Machine Learning

Zhiyao Xie, Hai Li, Xiaoqing Xu +2

IR drop constraint is a fundamental requirement enforced in almost all chip designs. However, its evaluation takes a long time, and mitigation techniques for fixing violations may…