44 citations · 71 across the 19 of their papers we have counts for
21 papers
GPUThor: Amplifying Rowhammer Attacks via Non-Uniform Patterns to Exploit ECC-Protected GPUs
Chris S. Lin, Joyce Qu, Aditya Rajeev +1
GDDR memory in GPUs is vulnerable to Rowhammer attacks, where rapid memory accesses induce bit flips in adjacent cells, enabling data tampering and privilege escalation. However, p…
zkComposer: Decomposing Proof Construction to Scale zkML
Pawan Kumar Sanjaya, Christina Giannoula, Valdy Oktavian +4
Zero-knowledge machine learning (zkML) enables a server to perform verifiable inference while keeping model parameters private from the client. However, existing zkML systems incur…
AutoPRAC: Automating Attack Discovery for PRAC-Based Rowhammer Defenses using Model Checkers
Joyce Qu, Gururaj Saileshwar
Per-Row Activation Counting (PRAC) in DDR5 is a specification to mitigate Rowhammer attacks by tracking activations per row and triggering mitigative refreshes when needed. However…
GPUBreach: Privilege Escalation Attacks on GPUs using Rowhammer
Chris S. Lin, Yuqin Yan, Guozhen Ding +4
NVIDIA GPUs with GDDR memories have been shown susceptible to Rowhammer-based bit-flips, similar to CPUs. However, Rowhammer exploits on GPUs have been limited to injecting untarge…
CLIP: Client-Side Invariant Pruning for Mitigating Stragglers in Secure Federated Learning
Anthony DiMaggio, Raghav Sharma, Gururaj Saileshwar
Secure federated learning (FL) preserves data privacy during distributed model training. However, deploying such frameworks across heterogeneous devices results in performance bott…
Yet Another Mirage of Breaking MIRAGE: Debunking Occupancy-based Side-Channel Attacks on Fully Associative Randomized Caches
Chris Cao, Gururaj Saileshwar
Recent work presented at USENIX Security 2025 (SEC'25) claims that occupancy-based attacks can recover AES keys from the MIRAGE randomized cache. In this paper, we examine these cl…
GPUHammer: Rowhammer Attacks on GPU Memories are Practical
Chris S. Lin, Joyce Qu, Gururaj Saileshwar
Rowhammer is a read disturbance vulnerability in modern DRAM that causes bit-flips, compromising security and reliability. While extensively studied on Intel and AMD CPUs with DDR…
CnC-PRAC: Coalesce, not Cache, Per Row Activation Counts for an Efficient in-DRAM Rowhammer Mitigation
Chris S. Lin, Jeonghyun Woo, Prashant J. Nair +1
JEDEC has introduced the Per Row Activation Counting (PRAC) framework for DDR5 and future DRAMs to enable precise counting of DRAM row activations using per-row activation counts.…
When Mitigations Backfire: Timing Channel Attacks and Defense for PRAC-Based RowHammer Mitigations
Jeonghyun Woo, Joyce Qu, Gururaj Saileshwar +1
Per Row Activation Counting (PRAC) has emerged as a robust framework for mitigating RowHammer (RH) vulnerabilities in modern DRAM systems. However, we uncover a critical vulnerabil…
AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures
Bo Fu, Leo Tenenbaum, David Adler +7
In recent years, several hardware-based countermeasures proposed to mitigate Spectre attacks have been shown to be insecure. To enable the development of effective secure speculati…
QPRAC: Towards Secure and Practical PRAC-based Rowhammer Mitigation using Priority Queues
Jeonghyun Woo, Chris S. Lin, Prashant J. Nair +2
JEDEC has introduced the Per Row Activation Counting (PRAC) framework for DDR5 and future DRAMs to enable precise counting of DRAM row activations. PRAC enables a holistic mitigati…
Time Will Tell: Timing Side Channels via Output Token Count in Large Language Models
Tianchen Zhang, Gururaj Saileshwar, David Lie
This paper demonstrates a new side-channel that enables an adversary to extract sensitive information about inference inputs in large language models (LLMs) based on the number of…
PrisonBreak: Jailbreaking Large Language Models with at Most Twenty-Five Targeted Bit-flips
Zachary Coalson, Jeonghyun Woo, Chris S. Lin +8
We study a new vulnerability in commercial-scale safety-aligned large language models (LLMs): their refusal to generate harmful responses can be broken by flipping only a few bits…
Teaching an Old Dog New Tricks: Verifiable FHE Using Commodity Hardware
Jules Drean, Fisher Jepsen, Edward Suh +3
We present Argos, a simple approach for adding verifiability to fully homomorphic encryption (FHE) schemes using trusted hardware. Traditional approaches to verifiable FHE require…
When Speculation Spills Secrets: Side Channels via Speculative Decoding In LLMs
Jiankun Wei, Abdulrahman Abdulrazzag, Tianchen Zhang +2
Deployed large language models (LLMs) often rely on speculative decoding, a technique that generates and verifies multiple candidate tokens in parallel, to improve throughput and l…
Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation
Aamer Jaleel, Stephen W. Keckler, Gururaj Saileshwar
This paper focuses on mitigating DRAM Rowhammer attacks. In recent years, solutions like TRR have been deployed in DDR4 DRAM to track aggressor rows and then issue a mitigative act…
The Mirage of Breaking MIRAGE: Refuting the HPCA-2023 Paper "Are Randomized Caches Truly Random?"
Gururaj Saileshwar, Moinuddin Qureshi
The HPCA-2023 paper "Are Randomized Caches Truly Random?" makes the claim that "MIRAGE is broken" while relying on two faulty assumptions: (1) starting from a severely compromised…
Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems
Jeonghyun Woo, Gururaj Saileshwar, Prashant J. Nair
As Dynamic Random Access Memories (DRAM) scale, they are becoming increasingly susceptible to Row Hammer. By rapidly activating rows of DRAM cells (aggressor rows), attackers can e…
Practical Timing Side Channel Attacks on Memory Compression
Martin Schwarzl, Pietro Borrello, Gururaj Saileshwar +3
Compression algorithms are widely used as they save memory without losing data. However, elimination of redundant symbols and sequences in data leads to a compression side channel.…
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
Gururaj Saileshwar, Moinuddin Qureshi
Shared processor caches are vulnerable to conflict-based side-channel attacks, where an attacker can monitor access patterns of a victim by evicting victim cache lines using cache-…
Lookout for Zombies: Mitigating Flush+Reload Attack on Shared Caches by Monitoring Invalidated Lines
Gururaj Saileshwar, Moinuddin K. Qureshi
OS-based page sharing is a commonly used optimization in modern systems to reduce memory footprint. Unfortunately, such sharing can cause Flush+Reload cache attacks, whereby a spy…