77 citations · 163 across the 20 of their papers we have counts for
6 papers · 1 filter
FLiMS: a Fast Lightweight 2-way Merger for Sorting
Philippos Papaphilippou, Wayne Luk, Chris Brooks
In this paper, we present FLiMS, a highly-efficient and simple parallel algorithm for merging two sorted lists residing in banked and/or wide memory. On FPGAs, its implementation u…
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator
Hongxiang Fan, Martin Ferianc, Zhiqiang Que +4
Recent advances in algorithm-hardware co-design for deep neural networks (DNNs) have demonstrated their potential in automatically designing neural architectures and hardware desig…
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments
Zhiqiang Que, Erwei Wang, Umar Marikar +10
This paper presents novel reconfigurable architectures for reducing the latency of recurrent neural networks (RNNs) that are used for detecting gravitational waves. Gravitational i…
Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions
Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk
This paper presents a novel, non-standard set of vector instruction types for exploring custom SIMD instructions in a softcore. The new types allow simultaneous access to a relativ…
Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator
Martin Ferianc, Zhiqiang Que, Hongxiang Fan +2
Neural networks have demonstrated their outstanding performance in a wide range of tasks. Specifically recurrent architectures based on long-short term memory (LSTM) cells have man…
High-Performance FPGA-based Accelerator for Bayesian Neural Networks
Hongxiang Fan, Martin Ferianc, Miguel Rodrigues +3
Neural networks (NNs) have demonstrated their potential in a wide range of applications such as image recognition, decision making or recommendation systems. However, standard NNs…