15 citations · 47 across the 14 of their papers we have counts for
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cs.DC2020★ 2 cited
ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics
Rohit Agrawal, Kapil Ahuja, Dhaarna Maheshwari +1
Routing of the nets in Field Programmable Gate Array (FPGA) design flow is one of the most time consuming steps. Although Versatile Place and Route (VPR), which is a commonly used…
cs.DC2018★ 1 cited
Parallel FPGA Router using Sub-Gradient method and Steiner tree
Rohit Agrawal, Chin Hao Hoo, Kapil Ahuja +1
In the FPGA (Field Programmable Gate Arrays) design flow, one of the most time-consuming step is the routing of nets. Therefore, there is a need to accelerate it. In a recent paper…