From the 1 of 6 linked papers with an AI index.
6 papers
From Patterns to Parsers: Automatic Generation of Efficient Hardware Parsers for FPGAs
Tushar Garg, Andrew Boutros
This work presents an open-source tool for automatically generating efficient hardware parsers from high-level specifications. It uses a parsing intermediate representation (PIR) t…
Jack of All Scales: A Versatile FPGA Tensor Block for MXFP Precisions
Marwan Mekhemer, Ahmed Elsousy, Balaji Venkatesh +4
The paper analyzes how current FPGA DSP blocks handle low‑precision microscaling floating‑point (MXFP) formats and proposes modest architectural changes to the DSP tensor mode so t…
Boosting FPGA Performance with Direct BRAM-DSP Paths
Jiajun Hu, Ruthwik Reddy Sunketa, Andrew Boutros +1
Efficient data movement between memory and compute units is a key performance bottleneck in modern FPGA designs, particularly for deep learning (DL) workloads. In typical FPGA arch…
Modeling, Optimizing and Exploring Multi-Die FPGA Routing Architectures
Amirhossein Poolad, Soheil Gholami Shahrouz, Andrew Boutros +1
Die stacking has enabled 2.5D FPGAs by integrating multiple active dice on a passive silicon interposer for improved yield and capacity, and paved the way for 3D architectures that…
Déjà Vu Packing: Optimizing FPGA Logic Clustering Runtime via Pattern Memoization
Milo Liebster, Amin Mohaghegh, Andrew Boutros
Implementing a digital circuit on an FPGA fabric requires clustering technology-mapped netlist primitives into coarser-granularity blocks that can be directly mapped to the physica…
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
Junius Pun, Xilai Dai, Grace Zgheib +4
Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices. For instance, FPGAs can efficiently implement ar…