92 citations · 102 across the 17 of their papers we have counts for
18 papers
VeriChat: An Agentic Conversational AI Assistant for Hardware Security Verification
Dipayan Saha, Khan Thamid Hasan, Shams Tarek +3
Hardware security verification is a multi-stage process in which engineers must navigate complex design analyses, threat considerations, and verification strategies. They often nee…
ChartZero: Synthetic Priors Enable Zero Shot Chart Data Extraction
Md Touhidul Islam, Yasir Mahmud, Sujan Kumar Saha +2
Automated data extraction from line charts remains fundamentally bottlenecked by extreme stylistic diversity and a severe scarcity of comprehensively annotated, real-world datasets…
CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt
Md Touhidul Islam, Sujan Kumar Saha, Farimah Farahmandi +1
Automating analog circuit design remains a longstanding challenge in Electronic Design Automation (EDA). While Transformer-based Large Language Models (LLMs) have revolutionized so…
Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
Tanvir Rahman, Shuvagata Saha, Ahmed Y. Alhurubi +3
Increasing system-on-chip (SoC) heterogeneity, deep hardware/software integration, and the proliferation of third-party intellectual property (IP) have brought security validation…
Assertain: Automated Security Assertion Generation Using Large Language Models
Shams Tarek, Dipayan Saha, Khan Thamid Hasan +3
The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property…
AI-Assisted Hardware Security Verification: A Survey and AI Accelerator Case Study
Khan Thamid Hasan, Md Ajoad Hasan, Nashmin Alam +3
As hardware systems grow in complexity, security verification must keep up with them. Recently, artificial intelligence (AI) and large language models (LLMs) have started to play a…
LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification
Md Ajoad Hasan, Dipayan Saha, Khan Thamid Hasan +5
The growing complexity of modern system-on-chip (SoC) and IP designs is making security assurance difficult day by day. One of the fundamental steps in the pre-silicon security ver…
DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
Zahin Ibnat, Paul E. Calzada, Rasin Mohammed Ihtemam +4
As large language models (LLMs) continue to be integrated into modern technology, there has been an increased push towards code generation applications, which also naturally extend…
SVAgent: AI Agent for Hardware Security Verification Assertion
Rui Guo, Avinash Ayalasomayajula, Henian Li +3
Verification using SystemVerilog assertions (SVA) is one of the most popular methods for detecting circuit design vulnerabilities. However, with the globalization of integrated cir…
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
Paul E. Calzada, Zahin Ibnat, Tanvir Rahman +5
Large Language Models (LLMs) are gaining popularity for hardware design automation, particularly through Register Transfer Level (RTL) code generation. In this work, we examine the…
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
Dipayan Saha, Shams Tarek, Hasan Al Shaikh +8
Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenge…
BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection
Shams Tarek, Dipayan Saha, Sujan Kumar Saha +1
The current landscape of system-on-chips (SoCs) security verification faces challenges due to manual, labor-intensive, and inflexible methodologies. These issues limit the scalabil…
ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification
Dipayan Saha, Hasan Al Shaikh, Shams Tarek +1
Current hardware security verification processes predominantly rely on manual threat modeling and test plan generation, which are labor-intensive, error-prone, and struggle to scal…
When Everyday Devices Become Weapons: A Closer Look at the Pager and Walkie-talkie Attacks
Pantha Protim Sarker, Upoma Das, Nitin Varshney +4
Battery-powered technologies like pagers and walkie-talkies have long been integral to civilian and military operations. However, the potential for such everyday devices to be weap…
LLM for SoC Security: A Paradigm Shift
Dipayan Saha, Shams Tarek, Katayoon Yahyaei +4
As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic devices, the task of incorporating security into an SoC design flow poses significant chal…
Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications
Hasan Al Shaikh, Mohammad Bin Monjil, Shigang Chen +4
The expansive globalization of the semiconductor supply chain has introduced numerous untrusted entities into different stages of a device's lifecycle. To make matters worse, the i…
Quantifiable Assurance: From IPs to Platforms
Bulbul Ahmed, Md Kawser Bepary, Nitin Pundir +9
Hardware vulnerabilities are generally considered more difficult to fix than software ones because they are persistent after fabrication. Thus, it is crucial to assess the security…
Defense-in-Depth: A Recipe for Logic Locking to Prevail
M Tanjidur Rahman, M Sazadur Rahman, Huanyu Wang +6
Logic locking has emerged as a promising solution for protecting the semiconductor intellectual Property (IP) from the untrusted entities in the design and fabrication process. Log…