9 papers
CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents
Peilong Zhou, Zhirong Chen, Cangyuan Li +4
Hardware engineering exposes coding agents to a form of long-horizon work that is difficult to capture with pass-at-k: progress is continuous, tool feedback is delayed and heteroge…
When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Kun Wang, Cangyuan Li, Kaiyan Chang +3
The growing complexity of modern chips poses significant challenges to hardware verification. In recent years, coverage-guided fuzzing has emerged as a promising approach for impro…
Alpha-RTL: Test-Time Training for RTL Hardware Optimization
Peilong Zhou, Zhirong Chen, Cangyuan Li +4
Large language models (LLMs) have shown increasing promise in generating functionally correct register-transfer-level (RTL) hardware designs. Recent systems improve further through…
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
Zhirong Chen, Kaiyan Chang, Zhuolin Li +8
Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically…
A System Architecture for Low Latency Multiprogramming Quantum Computing
Yilun Zhao, Yu Chen, Kaiyan Chang +4
As quantum systems scale, Multiprogramming Quantum Computing (MPQC) becomes essential to improve device utilization and throughput. However, current MPQC pipelines rely on expensiv…
ChipGPT: How far are we from natural language hardware design
Kaiyan Chang, Ying Wang, Haimeng Ren +5
As large language models (LLMs) like ChatGPT exhibited unprecedented machine intelligence, it also shows great performance in assisting hardware engineers to realize higher-efficie…