8 papers
Rtl2lean: Automated RTL-to-Lean Translation with Hierarchical Theorem Generation and Lemma Reuse
Hongqin Lyu, Junxing Dong, Yonghao Wang +3
Formal verification with interactive theorem provers can provide strong correctness guarantees for register transfer level designs, but applying it to existing SystemVerilog code r…
Arcane: An Assertion Reduction Framework through Semantic Clustering and MCTS-Guided Rule Exploring
Hongqin Lyu, Yonghao Wang, Zhiteng Chao +2
Assertion-based Verification (ABV) is essential for ensuring that hardware designs conform to their intended specifications. However, existing automated assertion-generation approa…
CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations
Yonghao Wang, Yang Yin, Hongqin Lyu +8
LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We pro…
From Indiscriminate to Targeted: Functionally Critical Signal-Driven Assertion Generation using LLMs for Efficient RTL Verification
Yonghao Wang, Hongqin Lyu, Boling Chen +9
Functional verification has become the most time-consuming phase in IC development, and Assertion-Based Verification (ABV) is key to reducing debugging time. However, existing LLM-…
AssertMiner: Module-Level Spec Generation and Assertion Mining using Static Analysis Guided LLMs
Hongqin Lyu, Yonghao Wang, Jiaxin Zhou +3
Assertion-based verification (ABV) is a key approach to checking whether a logic design complies with its architectural specifications. Existing assertion generation methods based…
AssertFix: Empowering Automated Assertion Fix via Large Language Models
Hongqin Lyu, Yunlin Du, Yonghao Wang +3
Assertion-based verification (ABV) is critical in ensuring that register-transfer level (RTL) designs conform to their functional specifications. SystemVerilog Assertions (SVA) eff…