2 papers
cs.CR2025
PoSyn: Secure Power Side-Channel Aware Synthesis
Amisha Srivastava, Samit S. Miftah, Hyunmin Kim +2
Power Side-Channel (PSC) attacks exploit power consumption patterns to extract sensitive information, posing risks to cryptographic operations crucial for secure systems. Tradition…
cs.LG2025
Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset
Anand Menon, Samit S Miftah, Shamik Kundu +7
Hardware verification is crucial in modern SoC design, consuming around 70% of development time. SystemVerilog assertions ensure correct functionality. However, existing industrial…