2 papers
cs.AI2026
When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering
Ziteng Hu, Jiachi Chen, Wenhao Lv +2
The rapid advancement of large language models (LLMs) has led practitioners to increasingly rely on them for answering questions about hardware description languages (HDLs). Becaus…
cs.AR2025
ViTAD: Timing Violation-Aware Debugging of RTL Code using Large Language Models
Wenhao Lv, Yingjie Xia, Xiyuan Chen +1
In modern Very Large Scale Integrated (VLSI) circuit design flow, the Register-Transfer Level (RTL) stage presents a critical opportunity for timing optimization. Addressing timing…