activity
20212024
collaborators

12 papers

cs.CR2024

Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction

Lennart M. Reimann, Yadu Madhukumar Variyar, Lennet Huelser +3

The MiG-V was designed for high-security applications and is the first commercially available logic-locked RISC-V processor on the market. In this context logic locking was used to…

cs.ET2024

A Fully Automated Platform for Evaluating ReRAM Crossbars

Rebecca Pelke, Felix Staudigl, Niklas Thomas +6

Resistive Random Access Memory (ReRAM) is a promising candidate for implementing Computing-in-Memory (CIM) architectures and neuromorphic circuits. ReRAM cells exhibit significant…

cs.CR2024

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL

Lennart M. Reimann, Anshul Prashar, Chiara Ghinami +4

In contemporary Electronic Design Automation (EDA) tools, security often takes a backseat to the primary goals of power, performance, and area optimization. Commonly, the security…

cs.AR2024

CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures

Rebecca Pelke, Jose Cubero-Cascante, Nils Bosbach +3

The demand for efficient machine learning (ML) accelerators is growing rapidly, driving the development of novel computing concepts such as resistive random access memory (RRAM)-ba…

cs.AR2023

Mapping of CNNs on multi-core RRAM-based CIM architectures

Rebecca Pelke, Nils Bosbach, Jose Cubero +3

RRAM-based multi-core systems improve the energy efficiency and performance of CNNs. Thereby, the distributed parallel execution of convolutional layers causes critical data depend…

cs.CR2023

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors

Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic +2

Despite its ever-increasing impact, security is not considered as a design objective in commercial electronic design automation (EDA) tools. This results in vulnerabilities being o…