3 papers
cs.AI2025
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine
Adarsh Gupta, Bhabesh Mali, Chandan Karfa
Recent advancements in the field of reasoning using Large Language Models (LLMs) have created new possibilities for more complex and automatic Hardware Assertion Generation techniq…
cs.AR2024
LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification
Karthik Maddala, Bhabesh Mali, Chandan Karfa
Writing SystemVerilog Assertions (SVA) is an important but complex step in verifying Register Transfer Level (RTL) designs. Conventionally, experts need to understand the design sp…
cs.CR2024
MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs
Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa
The design and synthesis of masked cryptographic hardware implementations that are secure against power side-channel attacks (PSCAs) in the presence of glitches is a challenging ta…