2 papers
cs.AR2020
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
SeyedRamin Rasoulinezhad, Siddhartha, Hao Zhou +3
We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the irst tier,…
cs.AR2017
Out-of-Order Dataflow Scheduling for FPGA Overlays
Siddhartha, Nachiket Kapre
We exploit floating-point DSPs in the Arria10 FPGA and multi-pumping feature of the M20K RAMs to build a dataflow-driven soft processor fabric for large graph workloads. In this pa…