activity
20172021
most citedDesign-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning

22 citations · 50 across the 6 of their papers we have counts for

collaborators

6 papers

eess.IV2021

Multi-Cycle-Consistent Adversarial Networks for Edge Denoising of Computed Tomography Images

Xiaowe Xu, Jiawei Zhang, Jinglan Liu +10

As one of the most commonly ordered imaging tests, computed tomography (CT) scan comes with inevitable radiation exposure that increases the cancer risk to patients. However, CT im…

eess.IV2020

Multi-Cycle-Consistent Adversarial Networks for CT Image Denoising

Jinglan Liu, Yukun Ding, Jinjun Xiong +6

CT image denoising can be treated as an image-to-image translation task where the goal is to learn the transform between a source domain (noisy images) and a target domain …

cs.LG2019★ 8 cited

Revisiting the Evaluation of Uncertainty Estimation and Its Application to Explore Model Complexity-Uncertainty Trade-Off

Yukun Ding, Jinglan Liu, Jinjun Xiong +1

Accurately estimating uncertainties in neural network predictions is of great importance in building trusted DNNs-based models, and there is an increasing interest in providing acc…

cs.CV2018★ 1 cited

PBGen: Partial Binarization of Deconvolution-Based Generators for Edge Intelligence

Jinglan Liu, Jiaxin Zhang, Yukun Ding +3

This work explores the binarization of the deconvolution-based generator in a GAN for memory saving and speedup of image construction. Our study suggests that different from convol…

cs.LG2018★ 19 cited

On the Universal Approximability and Complexity Bounds of Quantized ReLU Neural Networks

Yukun Ding, Jinglan Liu, Jinjun Xiong +1

Compression is a key step to deploy large neural networks on resource-constrained platforms. As a popular compression technique, quantization constrains the number of distinct weig…

cs.AR2017★ 22 cited

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning

Li Zhang, Bing Li, Jinglan Liu +2

At submicron manufacturing technology nodes, pro- cess variations affect circuit performance significantly. To counter these variations, engineers are reserving more timing margin…